Electronic devices

ABSTRACT

A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region.

This is a divisional of application Ser. No. 13/072,593 filed Mar. 25,2011, which is a divisional of application Ser. No. 10/538,857 filedDec. 22, 2005, which is a 371 of PCT/GB2003/005430 filed Dec. 12, 2003and which claims foreign priority to GB 0229191.2 filed Dec. 14, 2002,the disclosure of which is incorporated herein by reference.

This invention relates to electronic devices, especially organicelectronic devices, and methods suitable for forming such devices.

Semiconducting conjugated polymer thin-film transistors (TFTs) haverecently become of interest for applications in cheap, logic circuitsintegrated on plastic substrates (C. Drury, et al., APL 73, 108 (1998))and optoelectronic integrated devices and pixel transistor switches inhigh-resolution active-matrix displays (H. Sirringhaus, et al., Science280, 1741 (1998), A. Dodabalapur, et al. Appl. Phys. Lett. 73, 142(1998)). In test device configurations with a polymer semiconductor andinorganic metal electrodes and gate dielectric layers high-performanceTFTs have been demonstrated. Charge carrier mobilities up to 0.1 cm²Nsand ON-OFF current ratios of 10⁶-10⁸ have been reached, which iscomparable to the performance of amorphous silicon TFTs (H. Sirringhaus,et al., Advances in Solid State Physics 39, 101 (1999)).

One of the advantages of polymer semiconductors is that they lendthemselves to simple and low-cost solution processing. However,fabrication of all-polymer TFT devices and integrated circuits requiresthe ability to form lateral patterns of polymer conductors,semiconductors and insulators. Various patterning technologies such asphotolithography (WO 99/10939 A2), screen printing (Z. Bao, et al.,Chem. Mat. 9, 1299 (1997)), soft lithographic stamping (J. A. Rogers,Appl. Phys. Lett. 75, 1010 (1999)) and micromoulding (J. A. Rogers,Appl. Phys. Lett. 72, 2716 (1998)), as well as direct ink-jet printing(H. Sirringhaus, et al., UK 0009911.9) have been demonstrated.

Many direct printing techniques are unable to provide the patterningresolution that is required to define the source and drain electrodes ofa TFT. In order to obtain adequate drive current and switching speedchannel lengths of less than 10 μm are required. In the case of inkjetprinting this resolution problem has been overcome by printing onto aprepatterned substrate containing regions of different surface freeenergy (H. Sirringhaus et al., UK 0009915.0).

In patent application PCT/GB01/04421 a method is disclosed that allowsfabrication of polymer TFTs by a combination of direct write printingand embossing. The method is based on forcing a master containing anarray of sharp protruding wedges into a substrate containing at leastone polymer layer, and at least one conducting layer, and microcuttingthe conducting layer to form source and drain electrodes of the TFTs.The method disclosed can also be applied to multilayer structurescontaining more than one conducting layer, and allows the formation ofvertical field-effect transistor (FET) devices in which the transistorchannel is formed on a vertical side wall formed by the embossing stepand the channel length of the FET is defined by the thickness of adeposited insulating or semiconducting film, and not by a highresolution patterning step. This method allows for the low-costfabrication of FETs with submicrometer channel lengths.

In patent application PCT/GB01/04421 a method for defining aself-aligned gate electrode is also disclosed. The method is based onusing the topographical profile that is generated by an embossing stepthat define source-and-drain electrode to confine the deposition of thegate electrode.

In self-aligned device architectures the position of the gate electrodeis automatically adjusted and aligned with respect to source and drainelectrodes. This is very attractive for many circuit applications asthis minimizes the parasitic capacitance between source-drain and gateelectrodes. This is particularly important for printed devices where thewidth of deposited conducting electrodes and interconnects tends to belarge, i.e. on the order of 20-100 μm. Furthermore the positionalaccuracy of drop placement in a technique such as direct inkjet printingis usually not sufficient to achieve small overlap capacitance. Often inorder to ensure that the gate electrode overlaps with the active channelregion everywhere, and to allow for any statistical deviation of dropplacement a relatively large overlap is required. In a self-aligneddevice the gate electrode is confined automatically to the region of thechannel between source-and-drain electrodes without overlapping with theconducting source-drain electrode regions themselves, i.e. the area ofoverlap is approximately L W (L: channel length, W: channel width) asopposed to d W (d: width of the printed gate lines). In this way theparasitic overlap capacitance is reduced significantly.

According to a first aspect of the present invention there is provided amethod for forming an electronic device in a multilayer structurecomprising embossing a topographic profile into a substrate consistingof a first and second depressed (protruding) region, and a thirdprotruding (depressed) region separating the first and second region,comprising the additional step of depositing a solution of conductive orsemiconductive material into the first or second region. The method mayalso include selective modification of the surface energy of theembossed substrate prior to deposition of the conductive orsemiconductive material so as to reduce the wetting of the solution ofconductive or semiconductive material in the third region.

According to another aspect of the present invention there is provided amethod for forming a self-aligned electronic device in a multilayerstructure comprising defining a topographic profile in a first layerdepositing at least one additional, conformal layer on top the firstlayer, selectively modifying the surface energy of said additionallayer, and depositing a pattern of at least one additional layer inregistration with the topographic profile in the first layer.

According to another aspect of the present invention there is provided amethod for forming a vertical-channel field-effect transistor comprisingthe step of embossing a substrate containing at least one polymer layerand pushing a portion of a conducting electrode into the substrate, soas to form source and drain electrodes of a vertical-channel transistor.

According to yet another aspect of the present invention there isprovided a method for forming a surface energy pattern by embossing,that is used to direct the deposition of materials for formation of atleast one of the layers of a field effect transistor device.

According to another aspect of the present invention there is providedmethods and devices as set out in the accompanying claims.

Other aspects of the invention include devices formed by that and othermethods, and integrated circuits, logic-circuits, display circuits,sensing devices and/or memory device circuits comprising one or more ofsuch devices. Preferably the said devices are formed on a commonsubstrate. Preferably the said devices are formed in a common layer ofan organic material.

Preferred aspects of the present invention relate to methods by whichsolid state embossing can be used to fabricate polymer transistordevices and circuits.

Embodiments of the present invention will now be described, by way ofexample only, with reference to the accompanying drawings, in which:

FIGS. 1A-1F are schematic diagrams of one embodiment of the inventionthat allows definition of source and drain electrode of a planar FETwith high resolution.

FIG. 2 is a schematic diagram of a variant of the embodiment in FIG. 1,in which the embossing master has the shape of a sharp protruding wedge.

FIGS. 3A-3B are schematic diagram of a top-gate planar FET device with agate electrode that is self-aligned with the source and drainelectrodes.

FIGS. 4A-4C are schematic diagram of a bottom gate planar FET devicewith a gate electrode that is self-aligned with the source and drainelectrodes.

FIG. 5 is a schematic diagram of a bottom-gate (a) and top gate (b) FETdevice in which the electrodes in an upper layer are self-aligned by thetopographic profile generated by electrodes deposited in a lower layer.

FIGS. 6A-6C show device structure for a vertical-channel FET with aself-aligned gate electrode.

FIGS. 7A-7C show another device structure for a vertical-channel FETwith a self-aligned gate electrode.

FIGS. 8A-8C show a process for defining a surface energy pattern byembossing.

FIGS. 9A-9D show another process for defining a surface energy patternby embossing.

FIGS. 10A-10C show various processes for locally increasing thecapacitance of a dielectric layer.

FIG. 1 shows a schematic diagram of the use of embossing to define thecritical channel length of a FET device. The substrate 1 is a flexibleplastic substrate such as poly(ethleneterephtalate) (PET),polyethersulphone (PES) or polyethernaphtalene (PEN). Alternatively, thesubstrate may also be a rigid substrate, such as a glass substrate,coated with a polymer layer. The substrate is embossed by pressing anembossing tool 2 containing an array of protruding features into thesubstrate. The embossing step is performed at elevated temperatures,preferably close to the glass transition temperature of the substrate orthe topmost layer on the substrate. The embossing step may also beperformed by bringing the substrate 1 into its liquid phase. Preferably,the thickness of the polymer layer is chosen to be larger than theheight of the protruding features of the embossing tool, if the polymerlayer is thinner than the height of the protruding features of themaster, care needs to be taken to minimize damage of the embossing tool.After the embossing step a conductive ink 8 is deposited into theembossed grooves. The ink can be deposited in the form of droplets, suchas for example by inkjet printing, aerosol deposition, or spray coating,or as a continuous film, for example, by blade coating, spin coating, ordip coating. By capillary forces the deposition of the conductive ink isconfined to the grooves 3,4 on the substrate that define the source anddrain electrodes of the FET. No deposition occurs on top of the narrowridge 5 defining the channel length L of the device.

In order to enhance the confinement of the deposited ink into thegrooves the surface on top of the narrow ridge 5 and in the other flatregions of the substrate can be modified selectively to provide asurface energy contrast between the wetting surface in the grooves and alow-energy, dewetting surface on top of the ridge 5. This can beachieved by first preparing the whole surface of the substrate In a highenergy, wetting state by for example, using a polar polymer layer with ahigh surface energy as the embossed surface layer 1 of the substrate, orby exposing the substrate to an O₂ plasma or UV/ozone surface treatment.Subsequently, the substrate is brought in contact with a flat stamp 6inked with a self-assembled monolayer (SAM) 7 that is capable of bondingto functional groups on the surface of the substrate. Suitable SAMs arefor example octyltrichlorosilane C₈H₁₇SiCl₃ (OTS) orfiuoroalkyltrichlorosilane C_(n)F_(2n+1)C_(m)F_(2m)SiCl₃ or equivalentmethoxy silanes. Due to the topographic profile on the substrate the SAMis transferred selectively only in the flat regions of the substrate andon top of the ridge 5, rendering those surface regions non wetting forthe Ink to be deposited, while the bottom and side walls of the grooves3,4 remain wetting. This selective surface modification that is enabledby the topographical profile on the substrate provides a strongconfining force for the deposition of the conductive ink. Examples ofconducting inks include a conducting polymer such aspolyethylene-dioxythiophene doped with polystyrene sulfonic acid(PEDOT/PSS) or a conducting inorganic dispersion of metallicnanoparticles or chemical precursor solution for an inorganic metalformulated in a solvent. This surface modification method will bereferred to as “flat stamp method” in the following.

Alternatively, the selective surface modification making use of thetopographic profile on the surface can be defined by other techniquessuch as for example vacuum evaporation of a surface modifying layer atan oblique angle. If the substrate is not held normally with respect toa focussed beam of atoms or molecules evaporating from a source, but anoblique angle, the depressed regions of the substrate are shadowed bythe raised portions of the surface. The surface modifying material isonly evaporated onto the raised portions of the surface, and not ontothe depressed portions. It is possible that some surface modifyingmaterial is deposited onto sidewalls of the substrate separating theraised regions from the depressed regions.

After forming the source and drain electrodes 9,10 in this way thedevice is completed by depositing a layer of semiconducting material 11,such as regioregular poly(3-hexylthiopene) (P3HT) orpoly(dioctylfiuorene-co-bithiophene) (F8T2), a layer of gate dielectric12, such as a polymer layer of poly(methylmethacrylate (PMMA) and byprinting a pattern of conducting material for the gate electrode. Thegate electrode 13 can be formed from a conducting polymer such asPEDOT/PSS or a inorganic metal. Both the active semiconductor and thedielectric layer may also be patterned, such as to form an active layerisland of the device in order to reduce crosstalk between neighbouringdevices.

The channel length of the device which is defined by the width of theridge 5 is preferably less than 20 μm, preferably less than 5 μm, andmost preferably less than 1 μm. The minimum channel length is determinedby the resolution with which the pattern of protruding features on theembossing tool can be defined, and the mechanical properties of thepolymer substrate determining the maximum aperture ratio of pillarsembossed in the polymer substrate. A polymer that is suitable forachieving narrow ridges with good aperture ratio is PMMA.

, The depth of the grooves 3,4 can be used to vary the conductivity ofthe source-drain electrodes. In order to achieve good charge injectioninto the semiconducting active layer it is desirable to fill the grooves3,4 up to the top of the groove, such that the surface of the substrateafter deposition of the conductive electrodes is effectively planarized.In order to fabricate low resistance source and drain electrodes a deepgroove can be used in order to allow deposition of a very thickconductive film into the grooves.

The shape of the embossed grooves may have any form, such as a squareprofile (FIG. 1) or a triangular groove (FIG. 2). In the case of atriangular groove very high resolution patterning can be achieved. Inthis case the surface of the sharp ridge 5 is essentially a line ofarbitrarily small width. When the surface energy of such a ridge ismodified by bringing it Into contact with a flat stamp the width of thedewetting surface region that defines the channel length of thetransistor is limited only by the elastic deformation of the flatsubstrate, and by the diffusion of the SAM molecules on the surface ofthe substrate. Minimum width can be achieved, for example, by reducingthe pressure with which the flat stamp is pressed against the substrate,by reducing the time of contact, or by choosing a SAM molecule that hasa small diffusion coefficient on the surface of the substrate. Themethod in FIG. 2 allows easy fabrication of devices with submicrometerchannel length.

The methods disclosed above can be applied analogously to bottom gatedevices (where instead of the substrate it is the gate insulator that isembossed). In this case care needs to be taken that the depth of theembossed grooves is significantly smaller than the thickness of the gatedielectric in order to prevent electrical shorts of the gate dielectric.

According to another aspect of the invention a method for forming a FETdevice with a self-aligned gate electrode is disclosed. In order toachieve fast switching of FETs in a logic circuit it is important toreduce parasitic overlap capacitance due to geometric overlap betweenthe gate electrode and the source/drain electrodes. In a conventionaldevice architecture the overlap capacitance can only be reduced byreducing the linewidth of the gate electrodes and by accuratelyregistering the gate electrode with respect to the source/drainelectrodes. When printing techniques are used to define electrodes thisis often challenging. In order to achieve narrow line widths with atechnique such as inkjet printing droplets with small droplet volumesneed to be produced and the spreading of such droplets on the substratemust be controlled by a surface energy pattern that is accuratelyaligned with respect to the previously deposited patterns. In aself-aligned device the gate electrode is aligned automatically withrespect to the previously defined channel and is confined to the channelregion itself, not overlapping with the metallic source/drainelectrodes.

The invention is based on making use of a topographic surface profilethat is generated in a first layer to define a surface energy pattern inan upper layer that is self-aligned with respect to the topographicprofile in the first layer. It is an essential feature of the inventionthat one or more layers are deposited on top of the first layer withoutplanarising fully the topography in the first layer. In one embodimentof the invention (FIG. 3) in a first step a pattern of source/drainelectrodes is defined in a similar way as described in FIG. 1. However,in this case the grooves are not filled completely and a surfacetopography profile remains on the surface after deposition of theconductive material into the grooves 17,18.

The deposition conditions for the semiconducting material 19, and thegate dielectric material 20 are chosen such as to preserve thistopographic profile, i.e. a conformal coating is required. In the caseof solution deposition, this can be achieved by adjusting the surfaceenergy, and viscosity of the polymer solutions as well as the molecularweight of the polymers. Alternatively (in the case of a small moleculeorganic semiconductor such as pentacene) the layers can be depositedconformally by vacuum deposition techniques. Solution self-assemblytechniques such as the growth of polymer brushes on the surface can alsobe used.

If the source/drain electrodes are defined using embossed depressions inthe substrate the gate electrode needs to be confined to a wettingprotrusion on the surface of the gate dielectric. Different techniquescan be used to achieve this. In one embodiment of the invention thesurface of the gate dielectric is prepared in a non-wetting state forthe ink of the conductive gate electrode. The surface of the substrateis then laminated by bringing it into contact with a flat stampcontaining a surface modification material such as a SAM that is able tobond to a functional group on the surface, and has a tail that containsa polar group such as a carboxylic acid group. In contact with the stampthe top of the ridge 21 is then made wetting for the ink of theconducting gate material, while the bottom of the grooves remainnon-wetting, and self-aligned confinement of the gate ink droplets ontop of the ridge 21 can be achieved.

Alternatively, in an intermediate step a low-surface energy polymer25/26 is printed into the grooves on the surface of the gate dielectric.To help the confinement of this polymer Into the grooves the surface ofthe gate dielectric can be modified selectively by the techniquedescribed above using a dewetting surface modification layer 24. Afterthe deposition of the hydrophobic polymer the surface of the substrateis then made wetting, for example, by a low-energy O₂ plasma or UV/ozoneexposure. During this step the surface of the ridge 21 is made wettingagain. If the hydrophobic polymer is a fluoropolymer such as Teflon AF,the surface of the hydrophobic polymer remain low energy during thewetting treatment. In a final step the gate electrode is then printedand is confined in a self-aligned manner to the narrow ridge 21.Alternatively, the topographic profile of the hydrophobic polymer 25/26can be used to selectively modify the surface of the hydrophobic polymer25/26 to become hydrophobic again after the treatment that provideswetting properties to the ridges. This can be achieved by the flat stampmethod described above.

FIG. 4 shows an alternative device architecture for a bottom gate FETdevice with a self-aligned gate electrode. In this case the gateelectrode is defined first on the substrate using an embossedtopographic profile and a SAM layer 29 that renders the flat portions ofthe substrate wetting while the bottom and side walls of the groovesremain non-wetting. In this way confinement of the gate electrode to theridge defined by the embossing step is achieved. This is followed by theconformal, non-planarizing deposition of a dielectric layer 31, thesurface of which reflects the topographical profile embossed In thesubstrate. The surface of the dielectric is then prepared to be wetting(for example, by exposing the substrate to an O₂ plasma treatment or byusing a dielectric polymer that is wetting for the conducting ink forsource/drain electrodes, such as polyvinyiphenol in the case ofPEDOT/PSS). Subsequently the surface of the dielectric is modifiedselectively by bringing a flat stamp in contact with the surface. Thestamp contains a self-assembled monolayer 32 that renders the flatsurface regions 34 non-wetting. In this way ink deposition for thesource-drain electrodes 35,36 can be confined to the embossed grooves.The embossed ridge defines the channel of the device. The channel isself-aligned with the underlying gate electrode.

According to another aspect of the invention the topographic profilethat is required for the self-alignment of patterns in upper layers withrespect to patterns in tower layers can be generated by patterneddeposition of material onto the substrate itself without the need for anembossing step. In one embodiment a first pattern of electrodes isdefined on the surface (gate in bottom-gate structure in FIG. 5( a) andsource/drain in top-gate structure in FIG. 5( b)), for example with thehelp of a surface energy pattern 39 as disclosed in UK 0009915.0. Thethickness of the electrode material is preferably larger than 50 nm,most preferably larger than 150 nm. The material is preferably depositedin such a way that the thickness is uniform across the area of theelectrode, and that the thickness profile near the edge of the electrodeis abrupt. Subsequently, layers of dielectric 41 and semiconducting 46material are deposited conformally onto the substrate, in such a waythat the topographic profile generated by the first electrode pattern ispreserved on the surface for the self-aligned deposition of a second setof electrodes (source/drain electrodes 44/45 in FIG. 5( a) and gateelectrode 40 in FIG. 5( b)). Prior to the deposition of the second setof electrodes the surface of the substrate is modified selectively bybringing the substrate in contact with a flat stamp containing a SAMthat is transferred selectively onto the substrate and lowers thesurface energy. In some cases it might be necessary to deposit amechanical support layer 42, in order to avoid contact between the flatstamp and the substrate in the electrode regions. Such contact would beestablished due to sagging of the stamp, if the distance betweenprotruding features exceeds a critical distance, that depends on theheight of the protrusions and the rigidity of the stamp. Sagging canalso be prevented if mechanical support features are deposited on thelevel of the first set of electrodes, with similar topographyrequirements as for the first set of electrodes.

An alternative selective surface modification technique to the flatstamp method described above is as follows. On top of the corrugatedsurface to be modified selectively, a planarizing sacrificial continuouslayer is deposited by a technique such as, but not limited to by spincoating. Suitable planarizing polymer solutions are AccuFlo,commercially available from Honeywell. The substrate is then exposed toan etching step, for example to an O₂ plasma etching step, until thesurface of the raised portions of the underlying substrate layer isexposed again, while the indented regions remain protected by thesacrificial layer. Then the surface energy of the surface layer ismodified, for example by exposing the substrate to a vapour of aself-assembling molecule. During this step the indented portions of thesurface are protected by the sacrificial layer. Then the sacrificiallayer is removed in such a way that the surface energy in the modifiedregions remain unchanged. For example the sacrificial layer can beremoved by washing the substrate in a solvent in which the sacrificiallayer is soluble, but in which the surface layer is insoluble. In thisway selective surface energy patterning can be achieved without the needto bring the corrugated surface in physical contact with a flat stamp.

Alternatively, exposure to a plasma, for example, CF₄ plasma, may beused to alter the surface energy of the substrate or a subsequentlydeposited layer.

According to another aspect of the present invention a novelarchitecture is disclosed for a vertical channel field-effecttransistor, as well as a method for manufacturing such a device.

In a vertical TFT (see for example, A. Saitoh, at al. Jpn. J. Appl.Phys. 36, 668, (1997)) the channel length is defined by the thickness ofone of the deposited layers as opposed to a high-resolution patterningstep in the case of a planar TFT. In one possible configuration amesa-type structure is deposited first consisting of source and drainelectrode layers separated by a thin dielectric layer the thickness ofwhich determines the channel length of the TFT. A vertical side wall isthen formed by appropriate means such as a chemical etching process.Semiconducting and insulating layers are deposited onto the side wallsfollowed by a gate electrode. Vertical TFTs have been fabricated usinginorganic materials. They are useful because they allow formation ofsubmicrometer channel lengths without requiring expensive lithographictools, but offering enhanced circuit speed and drive currents.

Manufacturing of vertical polymer TFTs is difficult, mainly due toproblems associated with forming vertical sidewalls. Chemical etchingmethods for forming side walls pose problems because of the highsolubility of polymers in common organic solvents and the lack ofanisotropic etching mechanisms that in the case of inorganicsemiconductors cause etching to proceed faster in one crystallographicdirection than in others allowing formation of well defined facets. Moredirectional, physical etching methods such as reactive ion etchingsuffer from degradation of electrically functional polymers upon plasmaexposure.

In UK PCT/GB01/04421 a method is demonstrated by which vertical channelfield-effect transistors can be defined by microcutting a polymermultilayer structure with a sharp protruding wedge in order to define avertical side wall in the polymer multilayer structure exposingcross-section of the various layers in the multilayer structure. Themethod is based on forming a microcut groove in which during theembossing step materials transport occurs sideways in the plane of thesubstrate. The various layers are microcut, and pushed aside by plasticflow when the master penetrates into the substrate.

In the present method for forming a vertical field-effect devicematerials transport during the embossing step is primarily normal to thesubstrate, and not sideways. In one embodiment of the invention (FIG. 6)a conducting, layer 55 on a substrate 54 is embossed with a tool 56containing an array of protruding features with sharp edges. Thesubstrate 54 is preferably a flexible electrically insulating substratesuch as PET, PEN or PES, or a rigid substrate containing at least oneflexible polymer layer that is electrically insulating. The radius ofcurvature of the sharp edge is preferably less than 100 μm, mostpreferably less than 10 μm. Preferably, the protruding features have arectangular profile, although other protruding profiles are alsopossible. During the embossing step, a portion 57 of the conductinglayer 55 is pushed into the substrate, separating region 57 electricallyfrom the remaining conducting regions 58 and 59. In this way source anddrain electrodes of the device are defined. This structure is thencoated conformally with a layer of semiconducting material 60, and gatedielectric 61. Finally a gate electrode 63 is deposited. Preferably, thegate electrode is self-aligned with the source-drain electrodes. In oneembodiment of the invention the deposition of the gate electrode isconfined to the embossed groove with the help of a surface energybarrier 62, that is deposited selectively in the flat regions of thesubstrate using the flat stamp method. It is important that thethickness of the gate electrode in the groove is sufficient to allowaccumulation of the transistor channel along the full length of thetransistor channel.

In this structure the channel length is defined by the depth of theembossed groove. This can be controlled with the height of theprotrusion on the embossing master, in case the master is embossed toits maximum depth into the substrate, or with the embossing pressure,time and temperature, in case the master is embossed only partially intothe substrate, i.e., to less than the maximum depth. The method allowsconvenient definition of submicrometer channel lengths.

In the device structure shown in FIG. 6 vertical channels are formed onall sides of the embossed groove. For a given surface area of thedevice, the transistor current can be maximised by increasing the lengthof the side wall, for example by forming the protrusion on the embossingtool in the shape of a spiral.

In the device structure in FIG. 6 the overlap capacitance between thegate electrode 63 and source/drain electrode 58/59 is very small, whilethe overlap capacitance between the gate electrode and source/drainelectrode 57 is significant. When the device is used for fast switching,for example in a logic circuit or in an active matrix display, theelectrodes should be connected in such a way that the switchingperformance is optimised. In an active matrix display configuration, forexample, where any overlap capacitance between the pixel electrode andthe gate electrode is undesirable due to kick-back voltages appearing onthe pixel electrode upon switching of the gate voltages, electrode 58 or59 should be connected to the pixel electrode, while electrode 57 shouldbe connected to the data addressing line.

An alternative device structure is shown in FIG. 7. The structure issimilar to that in FIG. 6, but in this case the semiconducting material65 is part of the substrate 64 that is embossed. On top of thesemiconducting layer a conducting layer 66 is coarse patterned. Thethickness of the semiconducting layer needs to be as large as the depthto which the substrate is embossed, in order to ensure that the verticalside wall between source/drain electrodes 69 and 68 is fully formed fromsemiconducting material. The device is completed by deposition of a gatedielectric 71 and gate electrode 73. A surface energy barrier 72 can beused to help confining the gate electrode to the embossed groove.

One of the attractive features of the device configuration in FIG. 7 isthat during the embossing step the chains of the semiconducting polymercan be aligned along the direction of downward materials transport, i.e.along the direction of current flow in the device. This results inimproved field-effect mobilities and device performance.

The main advantage of the structure in FIGS. 7 and 6 compared to that inUK PCT/GB01/04421 is that in the former case efficient carrier injectionfrom the Source and drain electrodes in the channel can be achievedeasily, because the semiconducting layer and the source and drainelectrodes are in contact over a large area. In the device configurationdescribed in UK PCT/GB01/04421 at least one of the buried conductingelectrodes is only in contact with the semiconducting layer in across-sectional, vertical area, one side of which is determined by thesmall thickness of the buried metallic electrode. This may give rise toan enhanced parasitic source-drain contact resistance, particularly insituations where the ionisation potential of the semiconducting materialis larger, for hole conduction-based devices, or smaller for electronconduction-based devices, than the Fermi level of the conducting sourceand drain electrodes.

Electrical contact to the conducting layer in the depressed region canbe made by opening a via hole interconnection in the depressed region.In cases where the width of the depressed region is too narrow to open avia-hole interconnection without the risk of generating an electricalshort to the conducting layer in regions 58,59 the protruding wedge onthe embossing tool that defines the depressed region might, for example,be extended beyond the conductive layer. Subsequently, a solution ofconducting material can then be deposited into the depressed groove at asafe distance away from region 58,59, and the solution be transportedthrough the groove by capillary force and contacts the conductingmaterial 57 in the depressed region.

An alternative architecture for the device shown in FIGS. 6 and 7 is touse the depressed region of the substrate as a floating bridgeelectrode. In this case the embossing step is arranged in such a waythat the embossing tool pushes a portion of the conducting layer intothe substrate, and in this way interrupts the conductivity between afirst (undepressed) region of the conducting layer 58, and the depressedregion of the conducting layer, and between the first (undepressed)region of the conducting layer 58 and a second (undepressed) region ofthe conducting layer 59. The first and second region of the conductinglayer are then used as source-drain electrodes of the transistor and thedepressed region is used as a floating bridge electrode in the channelof the transistor. The floating bridge electrode shortens the channellength of the transistor. The active semiconducting channel region ofthe device only comprises two vertical channels formed along the twovertical side walls defined by the embossing step.

This device configuration does not require to make electrical contactwith the depressed region of the conducting layer. It also results invery small overlap capacitance between the gate electrode and both thesource and the drain electrode.

According to another aspect of the present invention a method isdisclosed by which embossing is used to define a surface energy patternfor the high-resolution solution deposition of conducting electrodes ona substrate.

In UK 0009915.0 a general method is disclosed for the high-resolutionpatterning of liquid semiconducting or conducting materials bydeposition from solution onto a substrate patterned into regions of highand low surface energy. The solution can be deposited by techniques suchas dip-coating, blade-coating or inkjet printing, and is repelled fromthe regions of low surface/interface energy, and deposits selectively inthe regions of high surface/interface energy on the substrate. Thesurface energy pattern is predefined by a broad range of experimentaltechniques, for example, by thermal transfer printing UK 0116174.4.

In the present invention we disclose a specific technique to define asurface energy pattern which is based on embossing a surface structureinto a sacrificial polymer layer.

In one embodiment of this aspect of the invention a hydrophobic polymerlayer 76 is deposited on top of a hydrophilic substrate (FIG. 8). Anexample of such a hydrophobic polymer might be a layer of polyimide witha thickness of 50 nm. The hydrophobic polymer might also have an alignedmolecular structure, for example imposed by mechanical rubbing or byexposure to linearly polarised light, in order to act as an alignmentlayer for a subsequently deposited polymer layer, in a second step asacrificial polymer layer 77 is deposited on top. Examples forsacrificial polymers are polyvinylphenol, novolak, orpolymethylmethacrylate (PMMA) with a thickness of 500 nm. Thesacrificial polymer layer is then embossed by pressing an embossing toolcontaining an array of protruding features into the substrate. In asubsequent step the embossed pattern is then transferred into thehydrophobic polymer layer by an etching step, such as an O₂ plasmaetching step, and/or a more directional reactive ion etching step,exposing the surface of the hydrophilic substrate in the areas that aredefined by the protruding features on the embossing tool. The etchprocess is stopped shortly after the surface of the substrate is exposedin the embossed regions. Due to the thickness difference betweenembossed and unembossed regions some sacrificial polymer remains in theunembossed regions protecting the surface of the hydrophobic polymerduring the etching. After removal of the sacrificial polymer layer forexample by washing of the substrate in a solvent in which thesacrificial polymer is soluble, the generated surface energy pattern canbe used for the high resolution definition of source-drain electrodes,or gate electrode and interconnects with narrow line widths. Forexample, the process to fabricate transistor devices on top of suchsurface energy patterns can be as described in detail in UK 0009915.0.

In another embodiment, the hydrophobic polymer is embossed directly,without the sacrificial polymer 77 on top. Also in this case, etching,such as plasma etching is used to remove the residual material ofhydrophobic polymer that remains in the embossed regions, and to exposethe substrate surface. In this case the surface of the hydrophobicpolymer is exposed to the etching medium, and care needs to be takenthat the etching process preserves a large contact angle differencebetween the surface of the hydrophilic substrate and the surface of theexposed substrate.

In an alternative embodiment, the surface energy pattern might also bedefined by a hydrophilic polymer, such as PVP or polyvinylalcohol onto ahydrophobic substrate such as PET. The hydrophilic polymer can bepatterned in same way as described above.

In another embodiment of the present invention (FIG. 9) a sacrificialpolymer such as PVP, PMMA or novolak is first deposited onto thesubstrate 82, and then embossed in order to generate regions ofdifferent thickness. An etching step such as wet etching, or preferablya plasma etching step is then used to expose the substrate surface inthe embossed regions. Then a self-assembled monolayer is deposited inthe exposed substrate regions by exposing the substrate to a vapour of amolecule containing a reactive group that is able to react with afunctional group that is present on the substrate surface and form aself-assembled monolayer (SAM) on the surface. For example, in the caseof a hydrophilic substrate such as glass alkylchlorosilanes, such asoctyltrichlorosilane (OTS), alkylmethoxysilanes orfiuoroalkylchlorosilanes bond to the hydroxyl groups on the surface andrender the surface hydrophobic. Prior to exposure to the self-assemblingmolecule the substrate might also be treated in order to increase thenumber of functional groups on the surface. Such treatment may be in theform of a chemical treatment or a plasma treatment. If the etching ofthe sacrificial layer is performed by O₂ plasma etching, the exposedregions of the substrate are automatically left with a large number ofhydroxyl groups.

After the substrate surface modification step the sacrificial polymerlayer is removed by washing it in a good solvent. Care needs to be takenthat the sacrificial polymer is removed completely from the substrate,and that no residues are left on the substrate, which might reduce thedifference in surface energy between the SAM modified and the bareregions of the substrate. This is particularly important in the case ofa high surface energy substrate that is prone to be coated with a thinlayer of lower energy polymer. This can be achieved by suitable choiceof the sacrificial polymer, for example in the case of a hydrophilicsubstrate such as glass, a polar polymer such as PVP is a suitablesacrificial polymer. Subsequently, devices are completed as describedabove.

This process to define surface energy patterns by embossing is not onlyapplicable for patterning of source and drain electrode on the substratelevel. It can be applied to reduce linewidth of interconnect lines, orto patterning of a semiconducting layer in form of an active layerisland. It can also be applied on upper levels of the device, forexample in order to fabricate source-drain electrodes in bottom gatestructures, or gate lines and interconnects with a narrow linewidthdefined by a surface energy pattern. In this case care needs to be takennot to damage the underlying layer during the embossing step, and theetch time needs to be controlled carefully since the underlying polymerlayers usually do not provide automatic etch stopping layers.

According to yet another aspect of the invention a method is disclosedby which a local change of the thickness of a dielectric layer can beused to locally increase the capacitance of the dielectric layer. Thismethod is useful to locally enhance the capacitance of the gatedielectric in the active area of the transistor, or in the area of adiscrete capacitor while in the remaining areas the capacitance of thedielectric layer remains at a low value. This minimizes any parasiticcapacitance in regions where a high capacitance is not needed. In FIG.10A a top-gate transistor is fabricated by depositing source-drainelectrodes 92 on top of a substrate 90, that might also contain asurface energy pattern 91 to improve resolution. Layers of thesemiconducting active material 93 and the gate dielectric 94 are thendeposited. After deposition the thickness of the gate dielectric isessentially uniform at least in the area of the device. Then the gatedielectric 94 is embossed as to reduce its thickness in the region abovethe active channel of the transistor. In order to achieve optimally lowparasitic source-drain-to-gate overlap capacitance the embossing toolneeds to be aligned with respect to the source-drain electrode, and thewidth of the region in which the dielectric layer thickness is reducedshould only be slightly larger, and generally be as close as possible tothe length of the channel between the source and drain electrodes.Subsequently, the conducting gate electrode 95 pattern is deposited. Thedifference to self-aligned schemes such as the one shown in FIG. 5B,that in the case of a local increase of gate dielectric capacitance thegate electrode does not need to be confined to the indented region ofthe gate dielectric 94. Even if the gate electrode deposition isunconfined, the overlap capacitance is low.

Similar methods can also be used to fabricate isolated discretecapacitors, for example for application in pixel capacitors in displays.In FIG. 10B, in addition to the capacitance in the active channelregion, the capacitance is also enhanced in the region of a pixelelectrode 97 connected to the drain electrode 92 of the TFT, and aground bus 98 line. Such capacitors are useful in active matrix displayapplications to reduce kickback voltage effects.

A related scheme is shown for the bottom gate TFT in FIG. 10C. In thiscase a topographic profile 99 is first generated on the substrate. Thetopographic profile can be generated by a range of techniques such as,but not limited to, direct-write deposition, lithographic patterning orembossing. The topographic profile is such that in the active region ofthe transistor the topographic profile is protruding. Then a gateelectrode pattern 100 is deposited over the protruding region in theactive channel region, and the adjacent indented regions. The device isthen completed by deposition of gate dielectric 101, patterned sourceand drain electrode 102 (possibly aided with the help of a surfaceenergy pattern 103) and semiconducting layer 104. The gate electrodeneeds to be deposited in such a way that the structure is effectivelyplanarized. This is possible for example by adjusting the formulation ofa spin-coated gate dielectric, or by using a blade coating technique,for the deposition of the gate dielectric that planarizes the surface ofthe gate dielectric layer.

The advantage of this structure is that the gate electrode does not needto be confined to the active channel region (i.e. the raised portion ofthe topographic profile), but still a small overlap capacitance can beachieved. This allows to use gate electrodes of large width, which isadvantageous for applications in which a high conductivity of the gateelectrode is required.

The device structures for the local increase of the capacitance of adielectric layer are merely illustrative, and can be applied to range ofdifferent device structures including both bottom and top-gatearchitectures.

In all of the above techniques, the embossing step is performedpreferrably at elevated temperature. The substrate that is embossedmight either be in a solid phase or in a liquid phase. In a preferredembodiment of the invention the embossing step is performed in the solidstate slightly below the glass transition temperature, T_(g) of thesubstrate or the layer to be embossed. The latter temperatures generallyare well known and can be found for instance in Polymer Handbook (Eds.,J. Brandrup, H. Immergut, E. A. Grulke, John Wiley & Sons., New York,1999), or can readily be determined according to standard thermalanalysis methods. Preferably, the embossing process according to thepresent invention is carried out in a temperature range from about 50°C. below to about 50° C. above T_(g), and more preferably from about 40°C. below to about 40° C. above that transition. Most preferred is thetemperature range from about 25° C. below to about 25° C. above T_(g).For semi-crystalline polymers the microstructuring method according tothe present invention is carried out in the temperature regime betweenabout the glass transition temperature, T_(g). and the meltingtemperature, T_(m). The latter temperatures generally are also wellknown and can also be found for instance in Polymer Handbook, or canreadily be determined according to standard thermal analysis methods.Preferably, the microstructuring process is carried out in a temperaturerange from about 50° C. below T_(g) to 1° C. below T_(m), and morepreferably from about 25° C. below T_(g) to 2° C. below T_(m). Mostpreferred is the temperature range from T_(g) to about 5° C. belowT_(m). Other processing parameters, such as the load that is appliedonto the master and time period during which it is applied, are lesscritical and are readily adjusted to ensure that the desired penetrationof the master through one or more of the layers is effected.

Embossing is performed at a temperature of 150° C. (PVP), 100° C.(Polystyrene), 105° C. (PMMA) for up to 60 min with a load of about 1kg/mm². Other processing conditions have also been shown to yieldsatisfactory results. Subsequently, the sample is cooled to roomtemperature before the pressure and the master are removed.

One of the other important features of the process is that the master orthe substrate to be embossed can be in contact with a soft rubberymaterial through which the pressure during the embossing is transmittedin a homogeneous way, such that a homogeneous depth of microgrooves isobtained across the substrate.

The microcutting tool has microcutting protrusions on it. These suitablytake the form of sharp protruding features, such as ridges,saw-tooth-type structures, spikes, and the like. The process of themanufacturing and the material of these microcutting tools are notcritical to the microcutting process. However, the material of which thetool is made should be sufficiently hard, and the protrusionssufficiently sharp that the tool is capable of cutting through thelayers. Where the tool is to cut through an upper layer of a multi-layerstructure the height h of the features should exceed the thickness d ofthe layer or layers that are to be cut Characteristic dimensions ofthese features, such as the feature height h, preferably are in therange between 1 mm and 1 nm. More preferably these characteristicdimensions are between about 100 μm and 5 nm, and most preferablybetween 10 μm and about 10 nm. To provide suitable sharpness the radiusof curvature of the protruding edges of these features should bepreferably less than 500 nm, more preferably less than 100 nm, and mostpreferably less than 10 nm.

The sharp protruding features may be of simple geometries (e.g.line-shaped ridges) or more complex such as interdigitated features.Examples of suitable geometries include arrays of conical or pyramidalprotrusions, and arrays of linear protrusions. One useful configurationis for the protrusions to be linear and parallel to each other.

The embossing tool suitably comprises at least one cutting edge, butpreferably a multitude of edges. The latter allows for fabrication of amultitude of devices in one single embossing/microcutting step. Theprotruding edges may all be of the same geometry or may differ from eachother. For instance, a microcutting tool according to the presentinvention may comprise arrays of line-shaped edges with which forexample pre-structured electrical-conductive layers on top of apolymeric substrate can be cut in one step leading to an array ofelectrodes e.g. for use in electrical devices such as thin-filmtransistors.

In another example the embossing master could be either planar orcylinder-shaped or could have whatever geometry is best suited for thedevice and device configuration to be fabricated as well the fabricationprocess. Cylinder-shaped microcutting tools are particularly useful asthey allow for embossing of a continuous flexible substrate in areel-to-reel process. Reel-to-reel fabrication may offer higherthroughput, and lower cost capability than a standard batch process. Inthis context it is of particular significance that the embossing isperformed preferably in the solid state, in which the embossed groovesretain their shape after the embossing tool is retracted. If theembossing were performed in the liquid phase, it would be necessary toreduce the substrate temperature before removing the microcutting tool,which would be difficult to achieve with a rolling cylindricalmicrocutting tool. The flexible tool could be constituted by a flexibleplastics structure, or could be a flexible sheet of another material,for instance a thin (e.g. 20 micron thick) sheet of silicon.

Large-area embossing tools according to one embodiment of the presentinvention can be fabricated for instance by combining a multitude ofembossing tools comprising the same or different relief structures.Cylinder-shape embossing tools may be fabricated by first producing aplanar tool which is subsequently rolled or bended.

Suitable masters can be made by a variety of methods known in the art,including, but not limited to anisotropic etching techniques,lithographic methods, electroplating, electroforming and the like.

Microcutting tools may be fabricated by first producing sharp featuresin e.g. a silicon wafer by anisotropic etching techniques. Thatmicroshaped wafer may be used as the tool itself, or subsequentlyreplicas of that wafer may be made for use as the tool. If the wafer isshaped as a negative of the desired tool then the tool may be moulded onthe wafer. If the wafer is a positive version of the desired tool then afirst replica of the wafer may be made, and then the tool may be formedas a replica of that first replica. The replicas are suitably made inmaterials such as thermoplastic and thermosetting polymers. This has theadvantage that sharp grooves can be etched into the original master,e.g. a silicon wafer, which is often a more straight-forward processthan etching sharp ridges. The polymeric replicas of such an originalmaster should be sufficiently hard and capable of cutting through thelayers to be structured. Accordingly, polymers used for replicaproduction preferably have a glass transition temperature larger than25° C., more preferably larger than 110° C. and most preferably largerthan 150° C. The latter temperatures generally are well known and can befound for instance in Polymer Handbook (Eds., J. Brandrup, H. Immergut,E. A. Grulke, John Wiley & Sons., New York, 1999). Preferably,high-glass transition, thermosetting resins are used for producingreplicated microcutting tools, such as cyanate ester resins (e.g.4,4′ethylidenediphenyl dicyanate andoligo(e-methylen-1,5-phenylencyanate) or epoxy resins such astetrafunctional tetraglycidyl diaminodiphenylmethane). The latter may bemixed before with an aromatic hardener such as 4,4′-diamino diphenylsulfone, DDS. In order to fabricate replicas, a polymer melt, solutionor pre-polymeric liquid as those listed above is cast, injection- orreaction moulded, and solidified in contact with the master structure bye.g. cooling, thermally or photochemically crosslinking. The originalmaster surfaces may be rendered non-adhesive, e.g. by rendering ithydrophobic, using suitable surface treatments such as chemicalmodification with self-assembling monolayers (e.g. silylation fromvapour phase using e.g. octadecyltrichlorosilane,perfluorodecyltrichlorosilane and allyltrimethoxysilane). Alternatively,release coatings or agents such as silicon oil may be employed on thesurface of the original master. It may also be useful to apply suchcoatings to the cutting surface of the tool.

As stated above, such polymeric replicas of the original masterstructure again can be used to produce 2^(nd), 3^(rd) or highergeneration replicas (“sub-masters”) which have either the same reliefstructure as the original master or a negative of it. Crucial is thatthe final microcutting tool comprises sharp protruding edges, such assharp ridges. In order to produce such “submasters” via e.g. embossing,injection- or reactive moulding, which subsequently can be used toreplicate the final microcutting tool, preferably polymeric materialsare employed that display good non-adhesive properties, such asperfluorinated polymers, polyolefins, polystyrene, or silicone rubbers(e.g. polydimethylsiloxane). Obviously, such submasters may be bended orrolled or shaped in whatever geometry is most desired depending on thedevice and device configuration to be fabricated in order to producecylinder-shaped microcutting tools or microcutting tools of more complexgeometries. For this purpose, it is useful to use flexible, polymericmaterials, such as polydimethylsiloxane or polyolefins for submasterproduction.

Submasters according to one embodiment of the present invention wereprepared by first producing a negative replica in polystyrene, PS(atactic polystyrene, M_(w)≈105 kg mol⁻¹, T_(g)≈100° C.; Aldrich). Forthis purpose, PS granulates were embossed at 180° C. with a siliconmaster comprising sharp grooves (height h≈10 mm, periodicity Λ=500 mm,edge angle α=70°; MikroMasch, Narva mnt. 13,10151, Tallinn, Estonia),applying onto the latter a nominal pressure of 300 g mm⁻² for 5 min (cf.Stutzmann, N., Tervoort, T. A., Bastiaansen, C. W. M. Feldman, & Smith,P. Adv. Mater. 12, 557 (2000)). Subsequently, 2^(nd) generationpolydimethylsiloxane (Sylgard silicone elastomer 184; Dow CorningCorporation) replicas according to one embodiment of the presentinvention were fabricated by poring the pre-polymeric liquid onto theseembossed PS films and curing it for 24 hours at room temperature in airatmosphere. The final microcutting tools were fabricated by producing a3^(rd) generation thermoset replica by first melting the cyanate esterresin Primaset PT15 (Lonza) at 110° C. for 30 min, casting this meltonto the structured PDMS films, curing it for 4 hours at 170° C. and,subsequently for 24 hours at 200° C., and removing at the end the PDMSreplicas from the cured, surface-structured thermoset.

In order to fabricate complex integrated circuits using microcutting themicrocutting tool might be fabricated with an arbitrary pattern ofwedges, that is able to define the critical device dimensions of anarbitrarily complex circuit. If such a complex master is defined byanisotropic etching of a crystalline wafer, sophisticated etchingtechniques such as corner compensation (cf. van Kampen, R. P. andWolffenbuttel, R. F. J. Micromech. Microeng. 5, 91 (1995), Scheibe, C.and Obermeier, E. J. Micromech. Microeng. 5, 109 (1995), Enoksson, P. J.Micromech. Microeng. 7, 141 (1997)) need to be used in order to ensurethat all protruding wedges of the tool that are supposed to cut acertain layer of the multilayer stack have the same height.

Alternatively, the microcutting tool may have a very simple wedgepattern, such as an array of parallel, linear wedges. In this case allcritical device dimensions need to be layout on a regular grid. However,circuits of arbitrary complexity can still be defined by appropriatelydefining the coarse pattern of the layer to be cut, and by depositingappropriate interconnections between the regularly spaced devices. Thisprocess is particularly suited for a reel-to-reel process based on acombination of direct printing and microcutting. In a first step aregular array of source-drain electrodes with suitable interconnectionsare written by a technique such as inkjet printing. Then the channel gapbetween source-drain electrodes is defined by microcutting. An activematrix display is an example where such a regular array of TFTs isparticularly useful.

It may be advantageous to hold the microcutting tool at the sametemperature as the multilayer structure during the forcing step, e.g.within 5° C. Alternatively, they may be at different temperatures: thusthe temperature of the microcutting tool may be more than 5° C.different from the temperature of the multilayer structure during theforcing step.

In one embodiment of the invention the conducting material is aconducting polymer, such as PEDOT/PSS or polyaniline (PANI). However,the processes and devices described herein are not limited to devicesfabricated with solution-processed polymers. Some of the conductingelectrodes of the TFT and/or the interconnects in a circuit or displaydevice (see below) may be formed from inorganic conductors, that can,for example, be deposited by printing of a colloidal suspension or byelectroplating onto a pre-patterned substrate. In devices in which notall layers are to be deposited from solution one or more PEDOT/PSSportions of the device may be replaced with an insoluble conductivematerial such as a vacuum-deposited conductor.

For the semiconducting layer any solution processable conjugatedpolymeric or oligomeric material that exhibits adequate field-effectmobilities exceeding 10⁻³ cm²/Vs, preferably exceeding 10⁻² cm²/Vs, maybe used. Suitable materials are regioregular poly-3-hexylthiophene(P3HT) or F8T2. For a review, see, for example H. E. Katz, J. Mater.Chem. 7, 369 (1997), or Z. Sao, Advanced Materials 12, 227 (2000). Otherpossibilities include small conjugated molecules with solubilising sidechains (J. G. Laquindanum, et al., J. Am. Chem. Soc. 120, 664 (1998)),semiconducting organic-inorganic hybrid materials self-assembled fromsolution (C. R. Kagan, at al., Science 286, 946 (1999)), orsolution-deposited inorganic semiconductors such as CdSe nanoparticles(B. A. Ridley, et al., Science 286, 746 (1999)). The semiconductingmaterial might also be a vacuum deposited organic semiconductor such aspentacene. The thickness of the semiconducting materials is preferrablyless than 200 nm, most preferrably less than 50 nm.

The semiconducting material can also be an inorganic semiconductor suchas thin film silicon deposited by vacuum or plasma depositiontechniques.

The gate dielectric is preferably a solution processed polymer layer,such as PVP, or PMMA. Alternatively, the gate dielectric might be avapour deposited inorganic dielectric, such as SiO₂ or Si₃N₄, or BaTiO₃.The thickness of the gate dielectric is preferably less than 2 μm, mostpreferably less than 500 nm.

Preferably, all materials are deposited by direct printing and solutionprocessing techniques, such as inkjet printing, soft lithographicprinting (J. A. Rogers at al., Appl. Phys. Lett. 75, 1010 (1999); S.Brittain et al., Physics World May 1998, p. 31), screen printing (Z.Bao, et al., Chem. Mat. 9, 12999 (1997)), and photolithographicpatterning (see WO 99/10939), offset printing, spin-coating, bladecoating or dip coating, curtain coating, meniscus coating, spraycoating, extrusion or plating. Ink-jet printing is considered to beparticularly suitable for large area patterning with good registration,in particular for flexible plastic substrates.

However, some of the materials might also be deposited from the vapourphase, or in another suitable way.

The device(s) can be fabricated on any substrate material, such asglass, or Perspex or a flexible, plastic substrate such aspolyethersulphone. Such a material is preferably in the form of a sheet,is preferably of a polymer material, and may be transparent and/orflexible. In the case of rigid substrate, such as glass, the substrateis preferably coated with a layer of polymer with a thickness oftypically 500 nm to 1 μm, in order to prevent damage to the embossingtool that might arise if it was pressed onto the surface of a rigidsubstrate.

Although preferably all layers and components of the device and circuitare deposited and patterned by solution processing and printingtechniques, one or more components such as a semiconducting layer mayalso be deposited by vacuum deposition techniques and/or patterned by aphotolithographic process.

When depositing polymer multilayer structures by successive solutiondeposition and printing steps, the integrity of the layer sequencerelies on the alternating deposition of polymer materials fromorthogonal solvents, in order to form, well controlled interfaces. Inparticular, it is important that the active interface between thesemiconducting and gate dielectric polymer is abrupt, and that in anycase the solvent sequence for the deposition of the multilayer structureis chosen such that the solubility of the previous layer in the solventused for the deposition of the next layer is sufficiently small.Techniques for building up multilayer structures from solution aredisclosed in PCT/GB00/04934.

Devices such as TFTs fabricated as described above may be part of a morecomplex circuit or device in which one or more such devices can beintegrated with each other and or with other devices. Examples ofapplications include logic circuits and active matrix circuitry for adisplay or a memory device, or a user-defined gate array circuit.

Any of the semiconducting or dielectric layers of the device may also bepatterned, for example by direct inkjet printing. In particular, thesemiconducting layer may be patterned into an active layer island inorder to reduce the crosstalk and leakage currents between neighbouringtransistors in a logic circuit or active matrix display.

The present invention is not limited to the foregoing examples. Aspectsof the present invention include all novel and/or inventive aspects ofthe concepts described herein and all novel and/or inventivecombinations of the features described herein.

The applicant draws attention to the fact that the present inventionsmay include any feature or combination of features disclosed hereineither implicitly or explicitly or any generalisation thereof, withoutlimitation to the scope of any definitions set out above. In view of theforegoing description it will be evident to a person skilled in the artthat various modifications may be made within the scope of theinventions.

What is claimed is:
 1. A method for solution deposition of at least onepattern of material on a substrate comprising: (a) depositing onto asurface of a substrate an intermediate layer, wherein the substrate isone of hydrophobic and hydrophilic and the intermediate layer is theother of hydrophilic and hydrophobic; (b) depositing a sacrificial layeronto a surface of the intermediate layer; (c) embossing the sacrificiallayer so as to define at least one depressed region and at least oneraised region; (d) etching the sacrificial layer and the intermediatelayer so as to reveal the surface of the substrate in the areas definedby the one or more depressed regions, and leaving the intermediate layerin the areas defined by the one or more raised regions; (e) removing anyremainder of the sacrificial layer in the areas defined by the one ormore raised regions; and (f) using the etched intermediate layer tocontrol the deposition of a solution of said material on to thesubstrate.
 2. A method as claimed in claim 1, wherein said at least onepattern of material is at least one conducting electrode.
 3. A methodfor solution deposition of at least one pattern of material on asubstrate comprising: (a) depositing a sacrificial layer onto a surfaceof the substrate; (b) embossing the sacrificial layer so as to define atleast one depressed region and at least one raised region; (c) etchingthe sacrificial layer so as to reveal the surface of the substrate inthe areas defined by the one or more depressed regions, and leaving amask layer in the areas defined by the one or more raised regions; (d)modifying the surface energy of the substrate in the regions leftexposed by the mask layer; (e) removing the mask layer in a secondetching step, which has substantially no further effect on the surfaceenergy of the substrate, so as to leave a surface energy pattern on thesurface of the substrate conformal to the initial embossing; and (f)using the surface energy pattern to control the deposition of a solutionof said material on to the substrate.
 4. A method as described in claim3, wherein modifying the surface energy of the substrate comprisesexposing the substrate to a vapour of a self-assembling monolayer.
 5. Amethod as described in claim 3, wherein modifying the surface energy ofthe substrate comprises exposing the substrate to an oxygen plasma orultra violet/ozone surface treatment
 6. A method as described in claim3, wherein modifying the surface energy of the substrate comprisesexposing the substrate to a carbon tetrafluoride plasma treatment.
 7. Amethod as claimed in claim 3, wherein removing the mask layer such thatthe surface energy of the modified regions is unchanged compriseswashing in a solvent in which the mask layer is soluble, but thesubstrate is insoluble.
 8. A method as claimed in claim 4, wherein theself-assembling monolayer is capable of reacting with a functional grouppresent on the substrate surface.
 9. A method as claimed in claim 8,further comprising treating the surface of the substrate so as toincrease the number of functional groups on the surface of thesubstrate.